The Computer’s Model of the Memory Cache LRU Unit of the Processor’s Core of the Architecture IA–32

Abstract

in the presented scientific research work the author solves the problem of synthesis of the functional logic of the work of the unit of LRU of the internal cache memory of the central processor under the conditions of misses, hits and filling the rows of the data block of the internal cache memory. The architecture of models of the logic of selection of row among the unreliable certain set for filling and the logic of row replacement management with full accuracy of the selected set of data blocks are analyzed. Minimization of completely and not fully defined switching functions is carried out : function of L=f(B) and function of B+ =f(L,B) selecting of sets of rows among reliable and forming values of bits В2 +В1 +В0 + of the LRU block taking into account the previous state of these bits. As a result of synthesis minimal logical equations that describe a certain functional logic of the actual work of the unit of reliability/LRU of the on-chip cache memory unit as components of the central processor architecture of IA – 32 are obtained.